A feature of semiconductor stacking is the construction of a complete circuit on two or more stacked tiers. Such stacked IC devices include separate dies stacked together to create the complete circuit where at least one die is part of and corresponds to a tier. In order for such stacked IC devices to function properly, it is desirable to detect that the tiers are electrically coupled.
Conventionally, verification of the electrical coupling between tiers in a three-dimensional stack has been done by testing the stacked IC devices using external software-based production tests, such as applying input signals to the circuitry and observing the resultant output signals. It is desirable, however, to test the coupling between tiers without using external test signals.
Thus, it is desirable to develop a technique for identification of coupling between semiconductor tiers where the technique is independent of software-based input sequencing and added input test signals.